Technical Field
The present disclosure generally relates to semi-floating gate devices for use in semiconductor memory applications.
Description of the Related Art
A FinFET is an electronic switching device in which a conventional planar semiconducting channel is replaced by a semiconducting fin that extends outward from a top surface of a silicon substrate. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence current flow from three surfaces instead of one. The improved control achieved with a FinFET design results in faster switching performance and reduced current leakage than is possible with a planar transistor. FinFETs are described in further detail in U.S. Pat. No. 8,759,874, and U.S. Patent Application Publication US2014/0175554, assigned to the same assignee as the present patent document.
A vertical GAA FET is a linear, or 1-D, device in the form of a nanowire, oriented transverse to planar front and back surfaces of the silicon substrate. The nanowire includes source, channel, and drain regions that are grown epitaxially. One or more annular gates surround the channel region, capacitively controlling current flow through the channel from all sides. GAA FETs are described in further detail in U.S. patent application Ser. Nos. 14/588,337 and 14/675,536, assigned to the same assignee as the present patent document.
Floating gate transistors are used in non-volatile semiconductor memory applications such as flash memory and electrically programmable read only memory (EPROM) devices. A conventional floating gate (FG) transistor memory cell is a variant of a metal-oxide-semiconductor field effect transistor (MOSFET) device. In a MOSFET, a voltage applied to a control gate electrode controls current flow in a channel between source and drain terminals. The control gate is separated from the channel by a gate dielectric. In a floating gate transistor, a second, floating, gate is inserted in the dielectric between the channel region and the control gate. The floating gate is thus electrically isolated, so that charge placed onto the floating gate is trapped. The control gate can then be used either to inject charge onto, or to extract charge from, the floating gate to change the bit state of the memory cell, via a tunneling effect. Depending on its polarity, charge trapped on the floating gate will then either permit or block current flow in the channel.
A semi-floating gate (SFG) transistor is shown schematically in FIG. 2a, and in cross-section in FIG. 2b, as described in “A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation,” P. F. Wang et al., Science v. 341, August 2013. The SFG transistor differs from a FG transistor in that the second gate is coupled to the drain, forming a p-n junction diode. Thus, the electric potential of the SFG transistor is not truly floating, but instead is semi-floating. In one implementation, the control gate is also extended to form an embedded tunneling FET (TFET) that biases the p-n diode accordingly, to charge or discharge the SFG transistor. Thus, the SFG transistor includes three devices in one: a MOS transistor, a p-n diode, and a TFET. A conventional SFG transistor is capable of operating at low voltages, less than 2.0 V, and high speeds, on the order of a nanosecond, to complete a write operation. Thus, SFG transistors appear to be promising in that they reduce power consumption while increasing the speed of volatile memory devices. However, a disadvantage of the SFG transistor shown in FIGS. 2a and 2b is that the extensions made to form the p-n diode and the TFET increase the footprint of the device, which limits the memory density of a SFG transistor array.